In the past, a general MOS transistor formed in a semiconductor device or an imaging device is a surface channel type in which a region under a gate electrode is formed of an impurity region of an opposite conductivity type to a source-drain region. In the surface channel MOS transistor, a channel formed of an inversion layer is formed on a semiconductor substrate surface by applying voltage to the gate electrode, in order to flow electric current between a source and a drain.
Such a general MOS transistor formed in a semiconductor device or an imaging device, particularly the surface channel MOS transistor in which a channel region is formed on a surface side of the semiconductor substrate, has a possibility that mobility and noise characteristics degrade due to a carrier trap that exists in the vicinity of an interface between the semiconductor substrate and a gate insulating film.
A buried-channel MOS transistor including a channel region formed at a position away from the surface of the semiconductor substrate is not influenced by the carrier trap that exists in the vicinity of the interface between the semiconductor substrate and the gate insulating film. However, an impurity whose ion is implanted in the channel region causes decrease of an impurity concentration due to segregation, pileup, diffusion, and the like of the impurity on an element separating region side of the channel region, because of influence of a heat process. Thereby, there is a possibility that the noise characteristics degrade due to reduction in the effective gate width.
Patent Literature 1 proposes a buried-channel MOS transistor in which a channel region is configured with a first impurity diffusion region formed by ion implantation from an oblique direction and a second impurity diffusion region formed on an entire surface of a region under a gate electrode, in a region contacting with an element separating region side. In the proposal, the formation of the first impurity diffusion region compensates for decrease of the impurity concentration which occurs on the element separating region side of the channel region, enabling elongation of the effective gate width, and achieving reduction of the noise.